Three-dimensional (3D) integration of IC devices promises to reduce system form factor through direct stacking and interconnection of chips, made by using different technologies, into a single system. For this 3D integration, the semiconductor wafers carrying the chips and being arranged on top of each other have to be electrically connected. Such 3D architectures and methods for interconnecting the wafers are well-known in the art (cf. the American patent US 2010/0225002 A1 and the American patent U.S. Pat. No. 7,683,459 B2).
In order to build such 3D architectures, the stacked semiconductor wafers must contain interconnects or through-base wafer vias, in particular through-silicon vias (TSV), in the form of metal, in particular copper, nails. One of the enabling technologies to achieve such TSV is the formation of trenches in the semiconductor wafer substrates which reach deep into but not completely through the semiconductor wafer material. As the semiconductor wafers are typically 300 to 800 μm thick, the trenches have a depth of about 50 to about 600 μm. They can have different cross-sections such as squares, rectangles, triangles, circles, ellipses, etc. with diameters of about 1 to 200 μm. The trenches are then filled with an electrically conductive material (e.g., copper) by various well-known deposition methods (e.g., electroplating; cf. the American patent 2010/0200412 A1).
Thereafter, the semiconductor wafers having the filled trenches are thinned by removing the semiconductor wafer material (e.g., silicon in the case of silicon wafer processing) from the backside of the wafer. This can involve gluing the frontside of the semiconductor wafer, i.e., the side to which the filled trenches open, to a carrier wafer and chemically mechanically polishing (CMP) the backside of the semiconductor wafer until the bottoms of the filled trenches are exposed. By way of this thinning process, the electrically conductive through-base wafer vias are formed.
Chemical mechanical planarization or polishing (CMP) is the primary process to achieve local and global planarity of integrated circuit (IC) devices. The technique typically applies CMP compositions or slurries containing abrasives and other additives as an active chemistry between a rotating substrate surface and a polishing pad under an applied load. Thus, the CMP process couples a physical process such as abrasion with a chemical process such as oxidation or chelation. It is not desirable for the removal or polishing of substrate materials to be comprised of purely physical or purely chemical action, but rather the synergistic combination of both in order to achieve a fast uniform removal. This way, the substrate material is removed until the desired planarity is achieved.
In the case of the thinning process, a CMP slurry capable of polishing semiconductor wafer material (e.g., silicon in the case of a silicon wafer) at a sufficiently high rate is required so that a grinding step before the CMP becomes superfluous. Additionally, the CMP slurry must remove the electrically conductive material of the through-base wafer vias (e.g., copper) at the same rate or nearly the same rate as it removes the semiconductor material (e.g., silicon), in order to avoid deleterious defects. This means, that the ratio of the removal rate (MRR) of copper to the MRR of silicon, i.e., the copper over silicon selectivity, should be close to 1 or ideally 1.
Thus, when CMP slurries over-polish copper layers they may create a depression or “dishing” in the copper vias and trenches. This problem is made worse with through-silicon vias since these have often have large diameters, e.g., 100 μm diameter. This feature distortion is unacceptable to lithographic and other constraints in the IC manufacturing process. Another feature distortion which is disadvantageous for the IC manufacturing process is “erosion”. Erosion is the topography difference between a field of dielectric and a dense array of copper vias or trenches. During CMP, the materials of the dense array may be removed or eroded at a faster rate than the surrounding field of dielectric which effect causes the topography difference.
Similar problems arise in the process of manufacturing through-based wafer vias, in particular TSV, when silicon oxide dielectric films such as silicon dioxide films prepared by low-pressure and high-pressure plasma chemical vapor deposition (LDP or HDP CVD) using monosilane-oxygen or tetraethylorthosilicate (TEOS)-oxygen plasmas are present. Such architectures are described, for example, in the American patent U.S. Pat. No. 7,678,696 B2. In this case, the MRRs should be high and the oxide over copper selectivity should be higher than 1.
The American patent application US 2010/0081279 A1 discloses a CMP slurry for the removal of copper and silicon in a process for manufacturing TSV. The CMP slurry comprises                an oxidizing agent such as periodic acid, perchloric acid, a persulfate salt or acid thereof, a permanganate salt or acid thereof, ozone, silver oxide or elemental fluorine,        a metal chelating agent such as glycine,        abrasives,        water-miscible solvents,        surfactants,        pH-adjusting agents to adjust the pH between 5 to 13,        corrosion inhibitors such as 1,2,4-triazole, benzotriazole, 6-tolyltriazole, totyltriazole, 1-(2,3-dicarboxypropyl)benzotriazole and branched-alkyl-phenol-substituted benzotriazole,        fluorine containing compounds such as ammonium fluoride or tetramethylammonium fluoride,        non-polymeric nitrogen-containing compounds such as ammonium hydroxide or ethanolamine, and        biological agents such as bactericides, biocides and fungicides.        
The CMP slurry can be tuned to exhibit high copper and silicon MRRs and selectivities of close to 1 or 1 at downforces of 7 psi (410 mbar). Astonishingly so, hydrogen peroxide is unsuitable for the prior art CMP slurry. Nothing is said about the silicon dioxide MRR and the copper over oxide selectivity.
However, it would be highly desirable to have CMP slurries available which can be tuned to exhibit high copper, silicon and silicon dioxide MRRs and copper over silicon selectivity of close to 1 or 1 and silicon dioxide over copper selectivity of greater than 1.
The American patent application US 2001/0054706 A1 discloses an etching solution for planarizing copper surfaces with a spin etch planarization process. The etching solution does not contain abrasives. It comprises oxidizing agents selected from hydrogen peroxide and nitric acid, depassivating co-reactants selected from the group consisting of phosphoric acid, sulfuric acid, nitric acid, oxalic acid, acetic acid and organic acids, and diffusion controlling additives such as 1,2,4-triazole, 1,2,3-triazole and tetrazole.
The American patent U.S. Pat. No. 6,974,777 B2 discloses CMP slurries for polishing substrates having low-k dielectric films of the dielectric constant of about 3.5 or lower, the said CMP slurries comprising abrasives, amphiphilic nonionic surfactants, oxidizing agent such as hydrogen peroxide or persulfates, complexing and chelating agents and corrosion inhibitors such as 1,2,3-triazole, 1,2,4-triazole and benzotriazole. The CMP slurries have a pH of 6 to 12. The amphiphilic nonionic surfactants can reduce the MRR of the low-k dielectric films while leaving the MRRs of other metal or oxide films substantially unchanged. The use of the CMP slurries in processes for through-base wafer vias, in particular TSV, is not described.
The American patent U.S. Pat. No. 6,936,543 B2 discloses CMP slurries for polishing substrates having copper films. The said CMP slurries have the same or a similar composition as the CMP slurries disclosed in the U.S. Pat. No. 6,974,777 B2. They reduce the dishing and the dielectric erosion of copper. They increase the copper over oxide selectivity while leaving the copper over tantalum selectivity substantially unchanged. The use of the CMP slurries in processes for through-base wafer vias, in particular TSV, is not described.